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description the cxk591000tm/ym/m is a high speed cmos static ram organized as 131,072-words by 9 bits. a polysilicon tft cell technology realized extremely low stand-by current and higher data retention stability. special feature are low power consumption and high speed. the cxk591000tm/ym/m is a suitable ram for portable equipment with battery back up and parity bit. features fast access time cxk591000tm/ym/m (access time) -55ll 55ns (max.) -70ll 70ns (max.) -10ll 100ns (max.) low standby current cxk591000tm/ym/m -55ll/70ll/10ll 24a (max.) low data retention current cxk591000tm/ym/m -55ll/70ll/10ll 14a (max.) single +5v supply: 5v 10%. low voltage date retention: 2.0v (min.) broad package line-up cxk591000tm/ym 8mm 20mm 32 pin tsop package cxk591000m 525mil 32 pin sop package function 131072 word 9 bit static ram structure silicon gate cmos ic ?1 cxk591000tm/ym/m -55ll/70ll/10ll e93x06-ps 131,072-word 9-bit high speed cmos static ram sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxk591000tm 32 pin tsop (piastic) cxk591000ym 32 pin tsop (piastic) cxk591000m 32 pin sop (piastic) block diagram i /o gate column decoder row decoder buffer buffer buffer v cc gnd i/o1 i/o9 oe we ce1 a10 a11 a9 a8 a15 a16 a14 a12 a7 a5 a6 a4 a3 a1 a0 a13 a2 ce2 i /o buffer memory matrix 1024 1152
?2 cxk591000tm/ym/m address input data input/output chip enable 1, 2 input write enable input output enable input power supply ground symbol description supply voltage input voltage input and output voltage allowable power dissipation operating temperature storage temperature soldering temperrature ?time v cc v in v i/o p d topr tstg tsolder ?.5 to +7.0 ?.5 * to v cc + 0.5 ?.5 * to v cc + 0.5 0.7 0 to +70 ?5 to +150 235 ?10 v v v w ? ? ? ?s item symbol rating unit absolute maximum ratings (ta = 25?, gnd = 0v) * v in , v i/o = ?.0v min. for pulse width less than 50ns. pin description a0 to a16 i/o1 to i/o9 ce1, ce2 we oe v cc gnd 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 i/o4 gnd cxk591000m vcc a15 ce2 we a13 a8 a9 a11 oe a10 ce1 i/o9 i/o8 i/o7 i/o6 i/o5 oe a10 ce1 i/o9 i/o8 i/o7 i/o6 i/o5 gnd i/o4 i/o3 i/o2 i/o1 a0 a1 a2 18 19 20 21 22 23 24 25 26 27 28 29 30 32 a11 a9 a8 a13 we ce2 a15 vcc a16 a14 a12 a7 a6 a5 a4 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 17 a2 a1 a0 i/o1 i/o2 i/o3 i/o4 gnd i/o5 i/o6 i/o7 i/o8 i/o9 ce1 a10 oe 18 19 20 21 22 23 24 25 26 27 28 29 30 32 a3 a4 a5 a6 a7 a12 a14 a16 vcc a15 ce2 we a13 a8 a9 a11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 17 cxk591000tm (standard pinout) cxk591000ym (mirror image pinout) 19 18 17 20 21 22 23 24 25 26 27 28 29 30 31 32 pin configuration (top view) h l l l l h h h h l h h l not selected not selected output disable read write high z high z high z data out data in i sb1 , i sb2 i sb1 , i sb2 i cc1 , i cc2 , i cc3 i cc1 , i cc2 , i cc3 i cc1 , i cc2 , i cc3 ce1 ce2 oe we mode i/o pin v cc current truth table : "h" or "l"
?3 cxk591000tm/ym/m supply voltage input high voltage input low voltage item symbol min. typ. max. unit v cc v ih v il 4.5 2.2 ?.3 * 5.0 5.5 v cc + 0.3 0.8 v v v dc recommended operating conditions (ta = 0 to +70?, gnd = 0v) * v il = ?.0v min. for pulse width less than 50ns. input leakage current output leakage current operating power supply current i li i lo i cc1 v in = gnd to v cc ce1 = v ih or ce2 = v il or oe = v ih or we = v il v i/o = gnd to v cc ce1 = v il , ce2 = v ih v in = v ih or v il i out = 0ma -55ll -70ll -10ll 0 to +70? 0 to +40? +25? ? ? 12 24 0.8 0.6 24 5 2.4 3 ? ma 8 50 45 40 +1 +1 17 100 80 70 ? ? ma ma ma item system min. typ. * max. unit test conditions electrical characteristics dc characteristics (v cc = 5v 10%, gnd = 0v, ta = 0 to +70?) * v cc = 5v, ta = 25? average operating current output high voltage output low voltage standby current i cc2 i cc3 i sb1 i sb2 v oh v ol min. cycle duty = 100% i out = 0ma cycle time 1s duty = 100% i out = 0ma ce1 0.2v ce2 3 vcc ?0.2v v il 0.2v v ih 3 vcc ?0.2v ce2 0.2v ce1 3 vcc ?0.2v ce2 3 vcc ?0.2v ce1 = v ih or ce2 = v il i ol = 2.1ma 2.4 0.4 v v i oh = ?.0ma
?4 cxk591000tm/ym/m input capacitance i/o capacitance item symbol test conditions min. typ. max. unit c in c i/o 7 8 pf pf v in = 0v v i/o = 0v input pulse high level input pulse low level input rise time input fall time input and output reference level -55ll -70ll/10ll v ih = 2.2v v il = 0.8v tr = 5ns tf = 5ns 1.5v c l * = 30pf, 1ttl c l * = 100pf, 1ttl item conditions output load conditions ac characteristics ac test conditions (v cc = 5v 10%, ta = 0 to +70?) * c l includes scope and jig capacitances. i/o capacitance (ta = 25?, f = 1mhz) note) this parameter is sampled and is not 100% tested. ttl c l test circuit
?5 cxk591000tm/ym/m item symbol -55ll min. max. min. max. min. max. -70ll -10ll unit t rc t aa t co1 t co2 t oe t oh t lz1 , t lz2 t olz t hz1 , t hz2 * t ohz * 55 15 10 5 55 55 55 30 25 25 70 15 10 5 70 70 70 40 25 25 100 15 10 5 100 100 100 50 35 35 ns ns ns ns ns ns ns ns ns ns read cycle time address access time chip enable access time (ce1) chip enable access time (ce2) output enable to output valid output hold from address change chip enable to output in low z (ce1, ce2) output enable to output in low z (oe) chip disable to output in high z (ce1, ce2) output disable to output in high z (oe) read cycle (we = "h") * t hz1 , t hz2 and t ohz are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. * t whz is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage level. item symbol -55ll min. max. min. max. min. max. -70ll -10ll unit t wc t aw t cw t dw t dh t wp t as t wr t wr1 t ow t whz * 55 50 50 25 0 40 0 0 0 10 25 70 60 60 30 0 50 0 0 0 10 25 100 70 70 40 0 60 0 0 0 10 30 ns ns ns ns ns ns ns ns ns ns ns write cycle time address valid to end of write chip enable to end of write data to write time overlap data hold from write time write pulse width address setup time write recovery time (we) write recovery time (ce1, ce2) output active from end of write write to output in high z write cycle
?6 cxk591000tm/ym/m address t aa t rc t oh data out previous data valid data valid address t aa t rc t lz2 t ohz t oe t olz ce1 oe data out high impedance data valid t co1 t hz t lz1 t hz1 t hz2 t co2 ce2 timing waveform read cycle (1) : ce1 = oe = v il , ce2 = v ih , we = v ih read cycle (2) : we = v ih
?7 cxk591000tm/ym/m address t aw t wc t cw t dh t whz t dw ce1 we data out high impedance data valid t ow ( * 2 ) ( * 2 ) oe data in t wr t as t wp ( * 1 ) t cw ce2 write cycle (1) : we control write cycle (2) : ce1 control address oe t wc t aw data valid t as t cw t wr1 t wp t dw t dh high impedance ce1 we data out data in t cw ( * 3 ) ce2
?8 cxk591000tm/ym/m * 1 write is executed when both ce1 and we are at low and ce2 is at high simultaneously. * 2 do not apply the data input voltage of the opposite phase to the output while i/o pin is in output condition. * 3 t wr1 is tested from either the rising edge of ce1 or the falling edge of ce2, whichever comes earlier, until the end of the write cycle. write cycle (3) : ce2 control address oe t wc t aw data valid t cw t wr1 t wp t dw t dh high impedance ce1 we data out data in t as t cw ( * 3 ) ce2
?9 cxk591000tm/ym/m data retention voltage data retention setup time recovery time v dr i ccdr1 i ccdr2 t cdrs t r * 1 0 to +70? 0 to +40? +25? v cc = 2.0 to 5.5v * 1 chip disable to data retention mode 2.0 0 5 0.5 0.8 * 2 5.5 14 3 1.4 24 v ? ? ns ms item symbol test conditions min. typ. max. unit data retention characteristics (ta = 0 to +70?) * 1 ce1 3 vcc ?0.2v, ce2 3 vcc ?0.2v (ce1 control) or ce2 0.2v (ce2 control) * 2 v cc = 5v, ta = 25? data retention current v cc = 3.0v * 1 v cc 4.5v 2.2v v dr ce1 gnd t cdrs data retention mode ce1 3 v cc ?0.2v t r data retention mode t r t cdrs ce2 0.2v v cc 4.5v 0.4v ce2 gnd v dr data retention waveform low supply voltage data retention waveform (1) (ce1 control) low supply voltage data retention waveform (2) (ce2 control)
?10 cxk591000tm/ym/m example of representative characteristics 4.5 4.75 5 5.25 5.5 0.6 0.8 1.0 1.2 1.4 0 20 40 60 80 0.8 0.9 1.0 1.1 1.2 0 20 40 60 80 0.6 0.8 1.0 1.2 1.4 t oe t aa , t co1 , t co2 ta = 25? i cc 1 i cc 2 (write) i cc 2 (read) v cc = 5.0v t oe t co1 , t co2 , t aa v cc = 5.0v 4.5 4.75 5 5.25 5.5 1.5 1.25 0.5 i cc 1 i cc 2 ta = 25? 1.0 0.75 04812 20 0 0.2 0.4 0.6 1.0 read 55ns 100ns 0.8 write vcc = 5.0v ta = 25? 16 70ns 0 100 200 300 400 0.6 1.0 1.2 1.4 1.6 1.8 2.0 t oe t aa , t co1 , t co2 v cc = 5.0v ta = 25? 0.8 supply current vs. supply voltage supply current vs. frequency access time vs. supply voltage access time vs. ambient temperature access time vs. load capacitance supply current vs. ambient temperature i cc1 , i cc2 ?supply current (relative value) i cc2 ?supply current (relative value) t aa , t co1 , t co2 , t oe ?access time (relative value) i cc1 , i cc2 ?supply current (relative value) t aa , t co1 , t co2 , t oe ?access time (relative value) t aa , t co1 , t co2 , t oe ?access time (relative value) ta ?ambient temperature [?] c l ?load capacity [pf] ta ?ambient temperature [?] v cc ?supply voltage [v] frequency (1/t rc , 1/t wc ) [mhz] v cc ?supply voltage [v]
?11 cxk591000tm/ym/m 1.2 0.8 4.5 4.75 5.0 5.25 5.5 1.4 1.2 1.0 0.8 0.6 1.4 1 2345 1.8 1.4 1.0 0.6 0 0.2 0.4 0.6 0 2.0 3.0 4.0 5.0 6.0 20 10 5 2 0.2 020 406080 1 0.5 0 204060 80 vcc = 5.0v vcc = 5.0v ta = 25? 1.2 1.0 0.8 0.6 vcc = 5.0v ta = 25? 0.8 vcc = 5.0v ta = 25? 1.1 1.0 0.9 v il , v ih 2.0 1.5 1.0 0.5 ta = 25? i sb1 i sb2 standby current vs. ambient temperature standby current vs. supply voltage i sb1 ?standby current (relative value) i sb2 ?standby current (relative value) v il , v ih ?input voltage (relative value) ta ?ambient temperature [?] v cc ?supply voltage [v] v ol ?output low voltage [v] output low current vs. output low voltage standby current vs. ambient temperature output high current vs. output high voltage input voltage level vs. supply voltage ta ?ambient temperature [?] v oh ?output high voltage [v] i oh ?output high current (ralative value) i sb1 , i sb2 ?standby current (relative value) v cc ?supply voltage (v) i ol ?output low current (ralative value)
?12 cxk591000tm/ym/m package outline unit: mm cxk591000tm cxk591000ym sony code eiaj code jedec code tsop-32p-l01 tsop032-p-0820 package structure package material lead treatment lead material package weight 42 alloy solder plating epoxy resin 32pin tsop (plastic) m 0.08 0.5 0.2 ?0.03 + 0.08 16 1 17 32 8.0 0.2 * 18.4 0.2 20.0 0.2 1.07 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.1 0.1 0.5 0.1 0?to 10 a 0.1 detail a note : * ?dimensions do not include mold protrusion. 0.3g sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 alloy tsop-32p-l01r tsop032-p-0820-b 32pin tsop (plastic) m 0.08 0.5 0.2 ?0.03 + 0.08 16 1 17 32 8.0 0.2 * 18.4 0.2 20.0 0.2 1.07 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.1 0.1 0.5 0.1 0?to 10 a 0.1 detail a 0.3g note: dimension * ?does not include mold protrusion.
?13 cxk591000tm/ym/m cxk591000m m 0.12 1.27 16 1 0.4 0.1 32 17 20.5 ?0.1 + 0.4 11.2 ?0.1 + 0.3 14.0 0.4 package structure package material lead treatment lead material package weight sony code eiaj code jedec code sop-32p-l02 sop032-p-0525 epoxy resin solder plating 42 alloy 1.2g 32pin sop (plastic) detail a 2.9 ?0.25 + 0.15 0.1 a 11.9 0.15 ?0.05 + 0.1 0.2 0.1 0.8 0.2 0?to 10

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